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1 datasheet synchronous step-down pwm controller ISL8117A the ISL8117A is a synchronous buck controller to generate pol voltage rails and bias voltag e rails for a wide variety of applications in industrial an d general purpose segments. its wide input and output voltage ranges make it suitable for telecommunication and after-market automotive applications. ISL8117A is a derivative from the isl8117 by replacing its clkout pin with comp pin to provide flexibility to customers to configure the voltage loop compensation externally. the ISL8117A uses the valley current modulation technique to bring a hassle-free power supply design with minimal number of components and complete protection from unwanted events. the ISL8117A offers programmable soft-start and enable functions along with a power-good indicator for ease of supply rail sequencing and other housek eeping requirements. in ideal situations, a complete power supply circuit can be designed with 10 external components and provide ov/oc/ot protections in a space conscious 16 ld 4mmx4mm qfn package. the package uses an epad to improve thermal dissipation and noise immunity. low pin count, less number of external components and default internal values, makes the ISL8117A an ideal solution for quick to market simple power supply designs. the ISL8117A uti lizes single resistor settings for other functions such as operating frequency and overcurrent protection. its current mode control with v in feed-forward enables it to cover various applications. the unique dem/skipping mode at light load dramatically lowers standby power consumption with consistent output ripple over different load levels. related literature ? ug049, ?ISL8117Aeval1z eval uation board user guide? ? ug050, ?ISL8117Aeval2z eval uation board user guide? features ? wide input voltage range: 4.5v to 60v ? wide output voltage range: 0.6v to 54v ? light-load efficiency enhancement - low ripple diode emulation mode with pulse skipping ?programmable soft-start ? supports prebiased output with sr soft-start ? programmable frequency: 100khz to 2mhz ?external sync ?pgood indicator ?forced pwm ? adaptive shoot-through protection ? no external current sense resistor - use lower mosfet r ds(on) ? functional pins with default design values - en, rt, ss/trk, mod/sync, lgate/ocs ? complete protection - overcurrent, overvoltage, ov er-temperature, undervoltage ? pb-free (rohs compliant) applications ? plc and factory automation ? industrial equipments ?security surveillance ? server and data centers ?switcher and routers ? telecom and datacom ?led panels figure 1. typical application figure 2. efficiency vin vout vcc5v rt mod sync fb ss trk en isen pgnd lgate ocs phase ugate boot vin 1 2 3 4 12 11 10 9 5 6 7 8 16 15 14 13 pgo od ext bias sgnd comp isl811 7a 84 86 88 90 92 94 96 98 100 0 2 4 6 8 10 12 14 16 output current (a) efficiency (%) v in = 24v v in = 36v v in = 18v v in = 48v v in = 60v caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2015. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. august 31, 2015 fn8752.0
ISL8117A 2 fn8752.0 august 31, 2015 submit document feedback table of contents ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 typical application schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 general description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 internal 5v linear regulator (vcc5v) and ex ternal vcc bias supply (ext bias) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 enable and soft-start operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 output voltage programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 tracking operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 light-load efficiency enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 prebiased power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 frequency synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 gate control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 adaptive dead time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 internal bootstrap diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 power-good indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 protection circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 over-temperature protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 feedback loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 layout considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 general powerpad design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 component selection guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mosfet considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 output inductor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 output capacitor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ISL8117A 3 fn8752.0 august 31, 2015 submit document feedback pin configuration ISL8117A (16 ld 4x4 qfn) top view ordering information part number ( notes 1 , 2 , 3 ) part marking temp. range (c) package (rohs compliant) pkg. dwg. # ISL8117Afrz 81 17afrz -40 to +125 16 ld 4x4 qfn l16.4x4a ISL8117Aeval1z high power evaluation board ISL8117Aeval2z low power evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged pr oducts employ special pb-free material sets , molding compounds/die attach materials and 100% matte tin plate plus anneal (e3 termination finish, which is rohs complian t and compatible with both snpb and pb-free soldering operation s). intersil pb-free products are msl classified at pb-free peak reflow temperatures th at meet or exceed the pb-free requirements of ipc/jedec j std -020. 3. for moisture sensitivity level (msl), please see device information page for ISL8117A . for more information on msl please see techbrief tb363 . table 1. table of key differences part number loop compensation clock output signal package isl8117 internal compensation without comp pin clock output signal on cl kout pin 16 ld 4x4 qfn ,16 ld htssop ISL8117A external compensation with comp pin no clock output signal 16 ld 4x4 qfn pin descriptions pin number pin name function 1 mod/sync dual function pin. connect this pin to vcc5v to select diode emulation mode with pulse skipping at light load. while connected to ground or floating, the controller operates in pwm mode at light load. connect this pin to an external clock for synchronization. the controller operates in pwm mode at light load when synchronized with an external clock. 2 pgood open-drain logic output used to indicate the status of output voltage. this pin is pulled down when the output is not wit hin 12.5% of the nominal voltage or the en pin is pulled low. 1 3 4 15 mod/sync pgood rt ss/trk en extbias vin boot 16 14 13 2 12 10 9 11 6 578 ugate phase isen vcc5v comp fb pgnd lgate/ocs sgnd
ISL8117A 4 fn8752.0 august 31, 2015 submit document feedback 3 rt a resistor from this pin to ground adjusts the switching frequency from 100khz to 2mhz. the switching frequency of the pwm controller is determined by the resistor, r t as shown in equation 1 . where f sw is the switching frequency in mhz. when this pin is tied to ground, the output frequency is set to 300khz. when this pin is tied to vcc5v or floating, the output frequency is set to 600khz. 4 ss/trk dual function pin. when used for soft-starting control, a soft-start capacitor is connected from this pin to ground. a regulated 2 a soft-starting current charges up the soft-start capacito r. value of the soft-start capacitor sets the output voltage ramp. when used for tracking control, an external supply rail is configured as the master and th e output voltage of the master supply is applied to this pin via a resistor divider. the output voltage will track the master supply voltage. 5 comp voltage error amplifier output. it sets the reference of the inner current loop. feedback compensation network is connected between the comp and fb pins. the comp pin ca n provide max 30ma source and sink current. when comp pin is pulled below 1v, ugate duty cycle reduces to 0%. 6 fb output feedback input. connect fb to a resistive voltage di vider from the output to sgnd to adjust the output voltage. 7 pgnd power ground connection. this pin should be connected to the sources of the lower mosfets and the (-) terminals of the external input capacitors. 8 lgate/ocs low-side mosfet gate driver output and oc set pin. connect a 1k to 30k resistor between this pin and ground to set th e overcurrent threshold. if there is no resistor connected from this pin to gnd, the overcurrent threshold is automatically set to the same point as a 10k resistor does. 9 vcc5v output of the internal 5v linear regulator. this output supplies bias for the ic, the low-side gate driver and the intern al boot circuitry for the high-side gate driver. the vcc5v pin must always be decoupled to power ground with a minimum of 4.7f ceramic capacitor placed very close to the pin. do not allow the voltage at vcc5v to exceed vin at any time. to prevent excessive current through the vcc5v pin to the vin pin, a resistor can be connected from the vin pin to the power supply. 10 isen current sense signal input. this pin is used to monito r the voltage drop across the lower mosfet for current loop feedback and overcurrent protection. 11 phase phase node connection. this pin is connected to the juncti on of the upper mosfet?s source, output filter inductor and lo wer mosfet?s drain. 12 ugate high-side mosfet gate driver output. 13 boot bootstrap pin to provide bias for high-side driver. the posi tive terminal of the bootstrap capacitor connects to this pin . the bootstrap diode is integrated to help reduce total cost and reduce layout complexity. 14 vin this pin should be tied to the input rail. it provides powe r to the internal linear drive circuitry and is also used by th e feed-forward controller to adjust the amplitude of the pwm sawtooth. decouple this pin with a small ceramic capacitor (0.1f to 1f) to ground. 15 extbias input from an optional external 5v bias supply. there is an internal switch from this pin to vcc5v. this switch closes and supplies the ic power, bypassing the internal linear regulator, when voltage at extbias is higher than 4.7v (typ). do not allow voltage at the extbias pin to exceed vin at any time. to prevent excessive current th rough the extbias pin to the vin pin, a resistor can be connected from the vin pin to the power supply. decouple this pin to ground with a sma ll ceramic capacitor (0.1f to 1f) when it is in use, otherwise tie this pin to ground. do not float this pin. 16 en this pin provides an enable/disable function. the output is disabled when the pin is pulled to ground. when the voltage on the pin reaches 1.6v, the output becomes active. when the pi n is floating, it will be enabled in default by internal pull-up . -sgnd epad this is the small-signal ground common to all control circuitr y. it is suggested to route this separately from the high current ground (pgnd). sgnd and pgnd can be tied together if there is one solid ground plane with no noisy currents around the chip. all voltage levels are measured with respect to this pin. epad at ground potential. epad is connected to sgnd internally. however, it is highly recommended to solder it directly to ground plane for better thermal performance and noise immunity. pin descriptions (continued) pin number pin name function r t 39.2 f sw ----------- 1.96 C ?? ?? k ? ? = (eq. 1)
ISL8117A 5 fn8752.0 august 31, 2015 submit document feedback block diagram 5vcc 5vcc boot ugate phase lgate/ocs pgnd pgnd adaptive dead time v/i sample timing por enable bias supplies reference fault latch ov/uv oc fb sw thres. pgood en vin vcc5v extbias mod/sync fb ss/trk isen 2a ss/trk ss/trk + - + - 0.6v ref + - 1.75v reference duty cycle ramp generator clock rt sgnd lgate/ocs lgate/ocs oc pwm current sample current sample same state for 2 clock cycles required to latch overcurrent fault vin 5vcc comp + - + - + - + - ( note 6 ) figure 3. block diagram
ISL8117A 6 fn8752.0 august 31, 2015 submit document feedback typical application schematics figure 4. ISL8117Aeval1z evaluation board schematic figure 5. ISL8117Aeval2z evaluation board schematic 5 & x9 & s9 4$ %8..(; 5 3.3v/6a 9287 & s9 5 n *1' & x9 4.5 - 60v 9,1 / x & x9 5 & q9 5 4% 8 ,6/$ 02'6<1& 3*22' 57 6675. &203 )% 3*1' /*$7(2&6 9&&9 ,6(1 3+$6( 8* %227 9,1 (;7%,$6 (1 6*1' 5 n & x9 5 n 5 n & x9 & s9 & x9 *1' 5 n
ISL8117A 7 fn8752.0 august 31, 2015 submit document feedback absolute maximum rating s thermal information vcc5v to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +5.9v extbias to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +5.9v vin to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +62.5v boot/ugate to phase . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vcc5v+0.3v phase and isen to gnd . . . . . . . . . . . . . -5v (<20ns)/-0.3v (dc) to +62.5v en, pgood, ss/trk, fb, comp to gnd . . . . . . . . . . -0.3v to vcc5v+0.3v lgate/ocs to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vcc5v+0.3v rt, mod/sync to gnd . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vcc5v+0.3v vcc5v short-circuit to gnd duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1s esd rating human body model (tested per js-001-2010) . . . . . . . . . . . . . . . . . . 4kv machine model (tested per jesd22-a115c) . . . . . . . . . . . . . . . . . . 300v charge device model (tested per jesd22-c101e). . . . . . . . . . . . . . . 2kv latch-up (tested per jesd78d; class ii, level a, +125c) . . . . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) 16 ld qfn package ( notes 4 , 5 ) . . . . . . . . 40 2.5 maximum junction temperature . . . . . . . . . . . . . . . . . . . .-55c to +150c maximum operating temperature . . . . . . . . . . . . . . . . . . .-40c to +125c maximum storage temperature. . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c v in to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 60v vcc5v to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.1v to 5.5v extbias to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.1v to +5.5v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications recommended operating conditions un less otherwise noted. refer to ? block diagram ? on page 5 and ? typical application schematics ? on page 6 . v in = 4.5v to 60v, or vcc5v = 5v 10%, c_vcc5v = 4.7f, t a = -40c to +125c, typical values are at t a = +25c, unless otherwise specified. boldface limits apply across the operating temperature range, -40c to +125c. symbol parameter test conditions min ( note 9 )typ max ( note 9 )unit v in supply v in input voltage range 4.5 60 v v in supply current i vinq shutdown current ( note 7 )en = 0 pgood is floating 5 10 a i vinop operating current ( note 8 ) pgood is floating 2.5 4 ma vcc5v supply ( note 6 ) v cc operation voltage v in = 12v, i l = 0ma 4.85 5.1 5.4 v internal ldo output voltage v in = 4.5v, i l = 30ma 4.1 4.4 v internal ldo output voltage v in > 5.6v, i l = 75ma 4.75 5.05 v i vcc_max maximum supply current of internal ldo v vcc5v = 0v, v in = 12v 120 ma extbias supply ( note 6 ) v ext_thr switch over threshold voltage, rising extbias voltage 4.5 4.7 4.9 v v ext_thf switch over threshold voltage, falling extbias voltage 4.2 4.5 4.65 v r ext internal switch on-resistance v in = 12v 1.5 undervoltage lockout v uvlothr undervoltage lockout, rising v in voltage, 0ma on vcc5v 3.7 3.90 4.2 v v uvlothf undervoltage lockout, falling v in voltage, 0ma on vcc5v 3.35 3.50 3.85 v en threshold v enss_thr en rise threshold v in = 12v 1.25 1.60 1.95 v v enss_thf en fall threshold v in = 12v 1.05 1.25 1.55 v v enss_hyst en hysteresis v in = 12v 180 350 500 mv soft-start current i ss ss/trk soft-start charge current ss/trk = 0v 2.00 a
ISL8117A 8 fn8752.0 august 31, 2015 submit document feedback default internal minimum soft-starting t ss_min default internal output ramping time ss/trk open 1.5 ms power-good monitors v pgov pgood upper threshold 109 112.5 115 % v pguv pgood lower threshold 85 87.5 92 % v pglow pgood low level voltage i_sink = 2ma 0.35 v i pglkg pgood leakage current pgood = 5v 20 150 na pgood timing t pgr v out rising threshold to pgood rising ( note 11 )1.1 5 ms t pgf v out falling threshold to pgood falling 75 s reference section v ref internal reference voltage 0.600 v reference voltage accuracy t a = 0c to +85c -0.75 +0.75 % t a = -40c to +125c -1.00 +1.00 % i fblkg fb bias current -40 0 40 na pwm controller error amplifiers input common-mode range v in = 12v 0 vcc5v - 2 v dc gain v in = 12v 88 db gbw gain-bw product v in = 12v 8 mhz sr slew rate v in = 12v 2.0 v/s comp v ol v in = 12v 0.4 v comp v oh v in = 12v 2.6 v comp sink current ( note 12 )v comp = 2.5v 30 ma comp source current ( note 12 )v comp = 2.5v 30 ma pwm regulator t off_min minimum off time 308 ns t on_min minimum on time 40 ns d v ramp peak-to-peak sawtooth amplitude v in = 20v 1.0 v v in = 12v 0.6 v ramp offset 1.0 v switching frequency f sw switching frequency r t = 36k 890 1050 1195 khz switching frequency r t = 16.5k 1650 2000 2375 khz switching frequency rt pin connect to gnd 250 300 350 khz switching frequency rt pin connect to vcc5v or float 515 600 645 khz v rt rt voltage r t = 36k 770 mv synchronization f sync sync synchronization range r t = 36k 1230 2200 khz electrical specifications recommended operating conditions un less otherwise noted. refer to ? block diagram ? on page 5 and ? typical application schematics ? on page 6 . v in = 4.5v to 60v, or vcc5v = 5v 10%, c_vcc5v = 4.7f, t a = -40c to +125c, typical values are at t a = +25c, unless otherwise specified. boldface limits apply across the operating temperature range, -40c to +125c. (continued) symbol parameter test conditions min ( note 9 )typ max ( note 9 )unit
ISL8117A 9 fn8752.0 august 31, 2015 submit document feedback diode emulation mode detection v modethh mod/sync threshold high ( note 12) 1.1 1.6 2.1 v v modehyst mod/sync hysteresis ( note 12) 200 mv v cross diode emulation phase threshold ( note 10 )v in = 12v -3 mv pwm gate driver i ugsrc upper drive source current 2000 ma i ugsnk upper drive sink current 2000 ma i lgsrc lower drive source current 2000 ma i lgsnk lower drive sink current 4000 ma r ug_up upper drive pull-up vcc5v = 5v 1.5 r ug_dn upper drive pull-down vcc5v = 5v 1.5 r lg_up lower drive pull-up vcc5v = 5v 1.0 r lg_dn lower drive pull-down vcc5v = 5v 0.8 t gr_up upper drive rise time c out = 1000pf 9.0 ns t gf_up upper drive fall time c out = 1000pf 8.0 ns t gr_dn lower drive rise time c out = 1000pf 7.0 ns t gf_dn lower drive fall time c out = 1000pf 6.1 ns overvoltage protection v ovth ovp threshold 116 121 127 % overcurrent protection i ocset-cs oc set current source lgate/ocs = 0v 9 10.5 11.5 a over-temperature t ot-th over-temperature shutdown 160 c t ot-hys over-temperature hysteresis 15 c notes: 6. in normal operation, where the device is supplied with voltage on the vin pin, the vcc5v pin provides a 5v output capable of 75ma (minimum). when the device is supplied by an external 5v supply on the extbias pin, the internal ldo regulator is disabled. the voltage at vcc5 v should not exceed the voltage at v in at any time. (refer to ? pin descriptions ? on page 3 for more details.) 7. this is the total sh utdown current with v in = 5.6v and 60v. 8. operating current is the supply current consumed when the device is active but not switching. it does not include gate drive current. 9. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. 10. threshold voltage at phase pin for turning off the bottom mosfet during dem. 11. when soft-start time is less than 4.5ms, t pgr increases. with internal soft-start (the fastest soft-start time), t pgr increases close to its max limit 5ms. 12. compliance to limits is assure d by characterization and design. electrical specifications recommended operating conditions un less otherwise noted. refer to ? block diagram ? on page 5 and ? typical application schematics ? on page 6 . v in = 4.5v to 60v, or vcc5v = 5v 10%, c_vcc5v = 4.7f, t a = -40c to +125c, typical values are at t a = +25c, unless otherwise specified. boldface limits apply across the operating temperature range, -40c to +125c. (continued) symbol parameter test conditions min ( note 9 )typ max ( note 9 )unit
ISL8117A 10 fn8752.0 august 31, 2015 submit document feedback typical performance curves oscilloscope plots are taken using the ISL8117Aeval1z evaluation board, v in = 18v to 60v, v out = 12v, i out = 20a unless otherwise noted. figure 6. shutdown current vs temperature figure 7. quiescent cu rrent vs temperature figure 8. vcc5v load regulation figure 9. vcc5v line regulation figure 10. switching freq uency vs temperature (r t = 36k ? ) figure 11. switching frequency vs v in temperature (c) i v i n q ( a ) 0 1 2 3 4 5 6 7 8 9 10 -40 -25 -10 5 20 35 50 65 80 95 110 125 i v i n o p ( m a ) temperature (c) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 0 1 2 3 4 5 6 0 20 40 60 80 100 120 load current (ma) vcc5v (v) 4.4 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 0 102030405060 v in (v) vcc5v (v) f sw (khz) temperature (c) 1000 1010 1020 1030 1040 1050 1060 1070 1080 1090 1100 -40 -25 -10 5 20 35 50 65 80 95 110 125 v in (v) f sw (khz) 0 50 100 150 200 250 300 350 0 5 10 15 20 25 30 35 40 45 50 55 60
ISL8117A 11 fn8752.0 august 31, 2015 submit document feedback figure 12. reference voltage vs temperature figure 13. normalized output voltage vs voltage on soft-start pin figure 14. ccm mode efficiency figure 15. dem mode efficiency figure 16. ccm mode load regulation figure 17. ccm mode line regulation typical performance curves oscilloscope plots are taken using the ISL8117Aeval1z evaluation board, v in = 18v to 60v, v out = 12v, i out = 20a unless otherwise noted. (continued) v r e f ( m v ) temperature (c) 595 596 597 598 599 600 601 602 603 604 605 -40 -25 -10 5 20 35 50 65 80 95 110 125 0 20 40 60 80 100 120 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 soft-start pin voltage (v) normalized output voltage (%) 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 v in = 18v v in = 24v v in = 36v v in = 48v v in = 60v i out (a) efficiency (%) 20 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 i out (a) efficiency (%) v in = 18v v in = 24v v in = 36v v in = 48v v in = 60v 20 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 2 4 6 8 101214161820 output current (a) regulation (%) v in = 36v v in = 48v v in = 60v v in = 18v v in = 24v -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 18 24 30 36 42 48 54 60 i o = 20a v in (v) regulation (%) i o = 10a i o = 0a
ISL8117A 12 fn8752.0 august 31, 2015 submit document feedback figure 18. input current comparison with mode = ccm/dem, v in = 48v figure 19. phase, lgate, and inductor current waveforms figure 20. output ripple, mode = ccm f igure 21. output ripple, mode = dem figure 22. start-up waveforms; mode = ccm, load = 0a, v in =48v figure 23. start-up waveforms; mode = dem, load = 0a, v in = 48v typical performance curves oscilloscope plots are taken using the ISL8117Aeval1z evaluation board, v in = 18v to 60v, v out = 12v, i out = 20a unless otherwise noted. (continued) 0.001 0.01 0.1 1 10 0.01 0.1 1 10 i in (dem) i in (ccm) i in (a) i out (a) i l 10a/div lgate 5v/div phase 50v/div 2s/div 4s/div v out 50mv/div v out 50mv/div no load, v in = 48v 20a load, v in = 48v 4s/div v out 50mv/div v out 50mv/div no load, v in = 48v 20a load, v in = 48v 1ms/div 4ms/div v out 5v/div phase 5v/div lgate 5v/div i l 10a/div dem to ccm transition boot cap refresh 4ms/div v out 5v/div phase 5v/div lgate 5v/div i l 10a/div boot cap refresh burst mode operation
ISL8117A 13 fn8752.0 august 31, 2015 submit document feedback figure 24. start-up waveforms; mode = ccm, load = 0a , v in = 48v figure 25. start-up waveforms; mode = dem, load = 0a, v in = 48v figure 26. tracking; v in = 48v, load = 0a , mode = ccm figure 27. frequency synchronization; v in = 48v, load = 0a , default f sw = 300khz, sync f sw = 330khz figure 28. load transient response; v in = 48v, 0a to 20a 1a/s step load, ccm mode figure 29. ocp response, output short-circuited from no load to ground and released, ccm mode, v in = 48v typical performance curves oscilloscope plots are taken using the ISL8117Aeval1z evaluation board, v in = 18v to 60v, v out = 12v, i out = 20a unless otherwise noted. (continued) 20ms/div v out 5v/div ss 2v/div en 5v/div pgood 5v/div 20ms/div v out 5v/div ss 2v/div en 5v/div pgood 5v/div 4ms/div ss 500mv/div v out 10v/div pgood 5v/div 2s/div sync 5v/div lgate 5v/div i l 10v/div 400s/div v out 200mv/div i out 10a/div 200ms/div v out 10v/div i l 20a/div ss 5v/div pgood 5v/div
ISL8117A 14 fn8752.0 august 31, 2015 submit document feedback functional description general description the ISL8117A integrates control circuits for a synchronous buck converter. the driver and protection circuits are also integrated to simplify the end design. the part has an independent enable/disable control line en, which provides a flexible power-up sequencing and a simple vin uvp implementation. the soft-sta rt time is programmable by adjusting the soft-start capacitor connected from ss/trk. the valley current mode control scheme with input voltage feed-forward ramp simplifies loop compensation and provides excellent rejection to input voltage variation. input voltage range the ISL8117A is designed to operate from input supplies ranging from 4.5v to 60v. the input voltage range can be effectively limited by the available minimum pwm off-time as shown in equation 2 . where, v d1 = sum of the parasitic voltage drops in the inductor discharge path, including the lower fet, inductor and pc board. v d2 = sum of the voltage drops in the char ging path, including the upper fet, inductor and pc board resistances. t off(min) = 308ns. the maximum input voltage and minimum output voltage is limited by the minimum on-time (t on(min) ) as shown in equation 3 . where, t on(min) = 40ns in ccm and 60ns in dem. internal 5v linear regulator (vcc5v) and external vcc bias supply (extbias) all the ISL8117A functions can be internally powered from an on-chip, low dropout 5v regulator or an external 5v bias voltage via the extbias pin. bypass the linear regulator?s output (vcc5v) with a 4.7f capacitor to the power ground. the ISL8117A also employs an undervoltage lockout circuit, which disables all regulators when vcc5v falls below 3.5v. the internal ldo can source over 75ma to supply the ic, power the low-side gate driver and charge the boot capacitor. when driving large fets at high switching frequency, little or no regulator current may be available for external loads. for example, a single large fet with 15nc total gate charge requires 15nc x 300khz = 4.5ma (15nc x 600khz = 9ma). also, at higher input voltages with larger fets, the power dissipation across the internal 5v will incr ease. excessive dissipation across this regulator must be avoided to prevent junction temperature rise. thermal protection may be triggered if die temperature increases above +160c due to excessive power dissipation. when large mosfets are used, an external 5v bias voltage can be applied to the extbias pin to alleviate excessive power dissipation. voltage at the extb ias pin must always be lower than the voltage at the vin pin to prevent biasing of the power stage through extbias and vcc5v. an external uvlo circuit might be necessary to guarantee smooth soft-starting. the internal ldo has an overcurrent limit of typically 120ma. for better efficiency, connect vcc5v to vin for 5v 10% input applications. enable and soft-start operation pulling the en pin high or low can enable or disable the controller. when the en pin voltage is higher than 1.6v, the controller is enabled to initialize its internal circuit. after the vcc5v pin reaches the uvlo threshold, ISL8117A soft-start circuitry becomes active. the internal 2a charge current begins charging up the soft-start capacitor connected from the ss/trk pin to gnd. the voltage error amplifier reference voltage is clamped to the voltage on the ss/trk pin. the output voltage thus rises from 0v to regulation as ss/trk rises from 0v to 0.6v. charging of the soft-start capacitor continues until the voltage on the ss/trk pin reaches 3v. typical applications for isl8 117a use programmable analog soft-start or ss/trk pin for tracking. the soft-start time can be set by the value of the soft-start capacitor connected from the ss/trk to gnd. inrush current during start-up can be alleviated by adjusting the soft-starting time. the typical soft-start time is set according to equation 4 : when the soft-starting time set by external c ss or tracking is less than 1.5ms, an internal soft-start circuit of 1.5ms takes over the soft-start. pgood will toggle to high when the corresponding output is up and in regulation. pulling the en low disables the pwm output and internal ldo to achieve low standby current. the ss/trk pin will also be discharged to gnd by an internal mosfet with 70 r ds(on) . output voltage programming the ISL8117A provides a precision 0.6v internal reference voltage to set the output voltage. based on this internal reference, the output voltage can thus be set from 0.6v up to a level determined by the input voltage, the maximum duty cycle and the conversion efficiency of the circuit. a resistive divider from the outp ut to ground sets the output voltage. the center point of the divider shall be connected to the fb pin. the output voltage value is determined by equation 5 . where r 1 is the top resistor of the feedback divider network and r 2 is the bottom resistor connected from fb to ground. v in min ?? v out v d1 + 1t C off min ?? frequency ? --------------------------------------------------------------- ----------- ?? ?? ?? v d2 v d1 C + ? (eq. 2) v in max ?? v out t on min ?? frequency ? ------------------------------------------------------------- - ?? ?? ?? ? (eq. 3) t ss 0.6v c ss 2 ? a ----------- ?? ?? = (eq. 4) v out 0.6v r 1 r 2 + r 2 -------------------- - ?? ?? ?? = (eq. 5)
ISL8117A 15 fn8752.0 august 31, 2015 submit document feedback tracking operation the ISL8117A can be set up to track an external supply. to implement tracking, a resistive divider is connected between the external supply output and ground. the center point of the divider shall be connected to the ss/trk pin of ISL8117A. the resistive divider ratio sets the ramping rati o between the two voltage rails. to implement coincident tracki ng, set the tracking resistive divider ratio exactly the same as the ISL8117A output resistive divider given by equation 5 on page 14 . make sure that the voltage at ss/trk is greater than 0.6v when the master rail reaches regulation. to minimize the impact of the 2a soft-start current on the tracking function, it is recommen ded to use resistors of less than 10k for the tracking resistive divider. when overcurrent protection (ocp) is triggered, the internal minimum soft-start circuit determ ines the ocp soft-start hiccup. light-load efficiency enhancement when mod/sync is tied to vcc5v, the ISL8117A operates in high efficiency diode emulation mode and pulse skipping mode in light-load condition. the inductor current is not allowed to reverse (discontinuous operation). at very light loads, the converter goes into diode emul ation and triggers the pulse skipping function. in pulse skipping mode, the upper mosfet remains off until the output voltage drops to the point the error amplifier output goes above the pulse skipping mode threshold. the minimum t on in the pulse skipping mode is 60ns. prebiased power-up the ISL8117A has the ability to soft-start with a prebiased output. the output voltage would not be yanked down during prebiased start-up. the pwm is not active until the soft-start ramp reaches the output voltage times the resistive divider ratio. overvoltage protection is alive during soft-starting. frequency selection switching frequency selection is a trade-off between efficiency and component size. low switching frequency improves efficiency by reducing mosfet switching loss. to meet the output ripple and load transient requ irements, operat ion at a low switching frequency would require larger inductance and output capacitance. the switching frequency of the ISL8117A is set by a resistor connected from the rt pin to gnd according to equation 1 on page 4 . the frequency setting curve shown in figure 30 assists in selecting the correct value for r t . frequency synchronization the mod/sync pin may be used to synchronize ISL8117A to an external clock. when the mod/sync pin is connected to an external clock, ISL8117A will synchronize to this external clock frequency. for proper operation, the frequency set by resistor r t should be lower than the external clock frequency. when frequency synchronization is in action, the controllers will enter forced continuous cu rrent mode at light load. gate control logic the gate control logic translates the pwm signal into gate drive signals providing amplification, level shifting and shoot-through protection. the gate driver has circuitry that helps optimize the ic performance over a wide range of operational conditions. as mosfet switching times can vary dr amatically from type to type and with input voltage, the gate control logic provides adaptive dead time by monitoring real gate waveforms of both the upper and the lower mosfets. shoot-thr ough control logic provides a 16ns dead time to ensure that both the upper and lower mosfets will not turn on simultan eously causing a shoot-through condition. gate driver the low-side gate driver is supplied from vcc5v and provide a 4a peak sink current and a 2a peak source current. the high-side gate driver is capable of delivering a 2a peak sink and source current. gate-drive voltage for the upper n-channel mosfet is generated by a flying capacitor boot circuit. a boot capacitor connected from the boot pin to the phase node provides power to the high-side mosfet driver. to limit the peak current in the ic, an external resistor may be placed between the boot pin and the boot capacitor. this small series resistor also damps any oscillations caused by the reso nant tank of the parasitic inductances in the traces of the board and th e fet?s input capacitance. at start-up, the low-side mosfet turns on first and forces phase to ground in order to charge the boot capacitor to 5v. after the low-side mosfet turns off, the high-side mosfet is turned on by closing an internal switch between boot and ugate. this figure 30. r t vs switching frequency f sw 0 500 1000 1500 2000 2500 3000 3500 0 20 40 60 80 100 120 140 160 180 200 r t (k) f sw (khz)
ISL8117A 16 fn8752.0 august 31, 2015 submit document feedback provides the necessary gate-to-source voltage to turn on the upper mosfet, an action that boosts the 5v gate drive signal above v in . the current required to drive the upper mosfet is drawn from the internal 5v regulator. for optimal emi performance or re ducing phase node ringing, a small resistor might be placed between the boot pin to the positive terminal of the bootstrap capacitor. adaptive dead time the ISL8117A incorporates an ad aptive dead time algorithm on the synchronous buck pwm contro ller that optimizes operation with varying mosfet conditio ns. this algorithm provides approximately 16ns de ad time between the switching of the upper and lower mosfets. this dead time is adaptive and allows operation with different mosfets without having to externally adjust the dead time using a resist or or capacitor. during turn-off of the lower mosfet, the lgate voltage is monitored until it reaches a threshold of 1v, at whic h time the ugate is released to rise. adaptive dead time circuitry monitors the upper mosfet gate voltage during ugate turn-off. once the upper mosfet gate-to-source voltage has dropped below a threshold of 1v, the lgate is allowed to rise. it is recommended to not use a resistor between ugate and lgate and the respective mosfet gates as it may interfere with the dead time circuitry. internal bootstrap diode the ISL8117A has an integrated bootstrap diode to help reduce total cost and reduce layout complexity. simply adding an external capacitor across the boot and phase pins completes the bootstrap circuit. the bootstra p capacitor can be chosen from equation 6 . where q gate is the amount of gate charge required to fully charge the gate of the upper mosfet. the ? v boot term is defined as the allowable droop in the rail of the upper drive. as an example, suppose an up per mosfet has a gate charge (q gate ) of 25nc at 5v and also assume the droop in the drive voltage over a pwm cycle is 200mv. based on the calculation, a bootstrap capacitance of at leas t 0.125f is required. the next larger standard value capacitance of 0.22f should be used. a good quality ceramic capacitor is recommended. the internal bootstrap schottky diode has a resistance of 1.5 (typ) at 800ma. combined with the resistance r boot , this could lead to the boot capacitor charging insufficiently in cases where the bottom mosfet is turned on for a very short period of time. if such circumstances are expect ed, an additional external schottky diode may be added from vcc5v to the positive of the boot capacitor. r boot may still be necessary to lower emi due to fast turn-on of the upper mosfet. power-good indicator the power-good pin can be used to monitor the status of the output voltage. pgood will be tr ue (open drain) 1.1ms after the fb pin is within 12.5% of the reference voltage. there is no extra delay when the pgood pin is pulled low. protection circuits the converter output is monitored and protected against overload, light load and undervoltage conditions. undervoltage lockout the ISL8117A includes uvlo protection, which keeps the device in a reset condition until a proper operating voltage is applied. it also shuts down the ISL8117A if the operating voltage drops below a predefined value. the controller is disabled when uvlo is asserted. when uvlo is asserted, pgood is valid and will be deasserted. overcurrent protection the controller uses the lower mosfet's on-resistance, r ds(on) , to monitor the current in the converter. the sensed voltage drop is compared with a threshold set by a resistor r ocset connected from the lgate/ocs pin to ground during the initiation stage before soft-start. during the in itiation stage, a 10.5a current source from the lgate/ocs pin creates a voltage drop on rocset. the voltage drop is then read and stored as the ocp comparator reference. r ocset can be calculated by equation 7 . where i oc is the desired overcurrent protection threshold and r cs is the value of the current sense resistor connected to the isen pin. the unit for r ds(on) is in m and for r cs is in k . if an overcurrent is detected, the upper mosfet remains off and the lower mosfet remains on until the next cycle. as a result, the converter will skip a pulse. when the overload condition is removed, the converter will resume normal operation. if an overcurrent is detected for 2 consecutive clock cycles, the ic enters in a hiccup mode by turning off the gate driver and entering soft-start. the ic will st ay off for 50ms before trying to restart. the ic will continue to cycle through soft-start until the overcurrent condition is removed. hiccup mode is active during soft-start, so care must be taken to ensure that the peak inductor current does not exceed the overcurrent threshold during soft-start. boot ugate phase vcc_5v vin ISL8117A figure 31. upper gate driver circuit c b r boot optional external schottky c boot q gate ? v boot ----------------------- - ? (eq. 6) r ocset r ds on ?? ?? i oc ?? 0.7 3.5r cs + ------------------------------------------ - k ? ?? = (eq. 7)
ISL8117A 17 fn8752.0 august 31, 2015 submit document feedback because of the nature of this current sensing technique, and to accommodate a wide range of r ds(on) variations, the value of the overcurrent threshold should repr esent an overload current about 150% to 180% of the maximum operating current. if more accurate current protection is desired, place a current sense resistor in series with the lower mosfet source. when ocp is triggered, the ss/trk pin is pulled to ground by an internal mosfet for hiccup restart. when configured to track another voltage rail, the ss/trk pin rises up much faster than the internal minimum soft-start ramp. the voltage reference will then be clamped to the internal minimum soft-start ramp. thus, smooth soft-start hiccup is achieved even with tracking function. for applications with large in ductor ripple current, it is recommended to use a larger r cs to reduce the current ripple into the isen pin to less than 26a, which is the ocp comparator hysteresis. otherwise, when the load current approaches to the ocp trip point, the ocp comparat or can trip and reset in one switching cycle. the overcurren t condition cannot last for 2 consecutive cycles to force the ic into hiccup mode. instead, the ic will run in a half frequency pwm mode leading to a larger output ripple. overvoltage protection the overvoltage set point is set at 121% of the nominal output voltage set by the feedback resistors. in the case of an overvoltage event, the ic will attempt to bring the output voltage back into regulation by keeping the upper mosfet turned off and the lower mosfet turned on. if the overvoltage condition has been corrected and the output vo ltage returns to 110% of the nominal output voltage, both upper and lower mosfets will be turned off until the output voltage drops to the nominal voltage to start work in normal pwm switching. over-temperature protection the ic incorporates an over-tempe rature protection circuit that shuts the ic down when a di e temperature of +160c is reached. normal operation resumes when the die temperature drops below +145c through the in itiation of a full soft-start cycle. during otp shutdown, the ic consumes only 100a current. when the controller is disabled, thermal protection is inactive. this helps achieve a very low shutdown current of 5a. feedback loop compensation to adapt the different applicatio ns, the controller is designed with an externally compensated error amplifier . to make loop stable with wide input voltage an d output current several design measures were taken. first, the ramp signal applied to the pwm comparator is proportional to the input voltage provided at the vin pin. this keeps the modulator gain constant with varying input voltages. next, the load current proportion al signal is derived from the voltage drop across the lower mosfet during the pwm time interval and is subtracted from the amplified error signal on the comparator input. this creates an internal current control loop. the resistor r cs connected to the isen pin sets the gain in the current feedback loop. the following expression estimates the required value of the current sense resistor depending on the maximum operating load current and the value of the mosfet r ds(on) as shown in equation 8. choosing r cs to provide 30a of current to the current sample and hold circuitry is recommended but values down to 2a and up to 100a can be used. figure 32 shows the valley current mode buck converter circuit. r cs i max ?? r ds on ?? ?? 30 ? a ---------------------------------------------- - ? (eq. 8) figure 32. valley current mode buck converter circuit gi r esr c o r o l q1 q2 v in fm ea vref v c slope d vo r 1 c 1 r 2 r 3 c 2 c 3 r s
ISL8117A 18 fn8752.0 august 31, 2015 submit document feedback in the current loop the control to output simplified transfer function is shown in equation 9 . where: r o is the load resistor c o is the output capacitor l is the inductor r s is the current sense resistor (the r ds(on) of low mosfet) v o is the output voltage t is the period of one switching cycle d is the duty cycle of upper mosfet v sl is the slope compensation voltage (peak voltage of the ramp) v in is the input voltage of the buck v c is the output of the error amplifier g i is the gain of the current sensor for ISL8117A: v sl = v in x 0.05 g i = 8k/r cs then the low frequency pole frequency is shown by equation 10 . the high frequency pole frequency is shown by equation 11 . the output capacitor esr (r esr ) zero frequency is shown by equation 12 . the output voltage is regulated by error amplifier ea. the ea compensation network parameters can be determined by compensating the current loop poles and zero so as to implement an ideal -20db/decade close loop gain with around 0.1f sw crossover frequency. if the crossover frequency f c << f l , a type 2 compensation network is enough to achieve the goal. since a strong slope compensation is used, the f l is usually not too high but close to f c . thus, a type 3 amplifier is still needed. to simplify the model, assuming c 3 << c 2 , the type 3 ea amplifier transfer function is simplified to equation 13 . the transfer function has two poles and two zeros. the first pole at the origin al at the frequency of f p1 = 1/2 r 1 c 2 . this is the frequency where the impedance of r 1 is equal to c 2 . the second pole is at the frequency of f p2 = 1/2 r 3 c 3 . the first zero is at the frequency of f z1 = 1/2 r 3 c 2 . the second zero is at the frequency of f z2 = 1/2 r 1 c 1 to achieve ideal compensation, it is recommended to make f z1 =f p ; f z2 = f l and f p2 = f z as shown in figure 33 . the close loop transfer function is then simplified to equation 14 . the crossover frequency is shown by equation 15 . loop design example is shown in the following: v in = 12v v out = 3.3v i out = 6a f sw = 300khz t = 3.3s v o ? v c ? ------ - r o r i k d ? ------------------ - 1 s ? z ------ + 1 s ? p ------ - + ?? ?? 1 s ? l ---- - + ?? ?? ------------------------------------------- - ? = (eq. 9) k d "" 1 r o k m r i ? -------------------- + = k m 1 d0.5 C ?? r i t l --- v sl v in -------- + ? ------------------------------------------------------ - = r i g i r s ? = ? p 2 ? f p 1 c o ------ - = 1 r o ------ - 1 k m r i ? -------------------- + ?? ?? ? = (eq. 10) ? l 2 ? f l k m r i ? l -------------------- == (eq. 11) ? z 2 ? f z 1 c o r esr ? ------------------------- - == (eq. 12) v c ? v o ? ------ - 1sr 3 c 2 + ?? 1sr 1 c 1 + ?? sr 1 c 2 1sr 3 c 3 + ?? --------------------------------------------------------------- ----- - = (eq. 13) g loop s ?? r o r i k d ? ------------------ - 1 s ? z ------ + 1 s ? p ------ - + ?? ?? 1 s ? l ----- + ?? ?? ------------------------------------------- - 1sr 3 c 2 + ?? 1sr 1 c 1 + ?? sr 1 c 2 1sr 3 c 3 + ?? --------------------------------------------------------------- ----- - ? ? = (eq. 14) r o r i k d ? ------------------ - 1 sr 1 c 2 ------------------- ? = f c r o r i k d ? ------------------ - 1 2 ? r 1 c 2 ---------------------- ? = (eq. 15) gain converter f p 0.1f sw f p2 f z2 f l figure 33. crossover frequency f z f z1 f modulator ea
ISL8117A 19 fn8752.0 august 31, 2015 submit document feedback d=v out /v in = 0.275 l = 3.3h c o = 200f r o = v out /i out = 0.55 r s = 14m r cs = 3k due to the use of ceramic capacitors, the output capacitor esr (r esr ) zero frequency is very high and can be ignored. then v sl = 0.6 and r i = 0.037 to make 0.1fs crossover frequency and make the gain -20db/decade use equation 21 . if r 1 = 49.9k, r 2 = 11k, r 3 = 70k, c 1 = 74p use equation 22 . to suppress the switching frequency noise, one more pole f p2 =1/2 r 3 c 3 can be inserted. the frequency of this pole should be f c << f p2 << f sw select equation 23 then c 3 = 23p layout guidelines careful attention to layout requirements is necessary for successful implementation of an ISL8117A based dc/dc converter. the ISL8117A switches at a very high frequency and therefore the switching times are very short. at these switching frequencies, even the shortest trace has significant impedance. also, the peak gate drive curre nt rises significantly in an extremely short time. transition speed of the current from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, generate emi and increase device overvoltage stress and ringing. careful component selection and proper pc board layout minimizes the magnitude of these voltage spikes. there are three sets of critical components in a dc/dc converter using the ISL8117A: the controller, the switching power components and the small signal components. the switching power components are the most cr itical from a layout point of view because they switch a large amount of energy, which tends to generate a large amount of no ise. the critical small signal components are those connected to sensitive nodes or those supplying critical bias currents. a multilayer printed circuit board is recommended. layout considerations 1. the input capacitors, upper fet, lower fet, inductor and output capacitor should be plac ed first. isolate these power components on dedicated areas of the board with their ground terminals adjacent to one another. place the input high frequency decoupling ceramic capacitors very close to the mosfets. 2. if signal components and the ic are placed in a separate area to the power train, it is recommend to use full ground planes in the internal layers with shared sgnd and pgnd to simplify the layout design. otherwise, use separate ground planes for power ground and small signal ground. connect the sgnd and pgnd together close to the ic. do not connect them together anywhere else. 3. the loop formed by the input capacitor, the top fet and the bottom fet must be kept as small as possible. 4. ensure the current paths from the input capacitor to the mosfet, to the output inductor and the output capacitor are as short as possible with ma ximum allowable trace widths. 5. place the pwm controller ic close to the lower fet. the lgate connection should be short and wide. the ic can be best placed over a quiet ground area. avoid switching ground loop currents in this area. 6. place vcc5v bypass capacitor very close to the vcc5v pin of the ic and connect its ground to the pgnd plane. 7. place the gate drive componen ts - optional boot diode and boot capacitors - together near the controller ic. 8. the output capacitors should be placed as close to the load as possible. use short wide copper regions to connect output capacitors to load to avoid inductance and resistances. k m 1 d0.5 C ?? r i t l --- v sl v in -------- + ? ------------------------------------------------------ - 1 0.275 0.5 C ?? 0.037 3.3 ? 3.3 ? ----------- - ? 0.05 + --------------------------------------------------------------- ----------------------- 24 == = (eq. 16) k d 1 r o k m r i ? -------------------- + 1 0.55 24 0.037 ? --------------------------- - + 1.62 == = (eq. 17) g dc r o r i k d ? ------------------ - 9.18 = = (eq. 18) ? p 1 c o ------ - 1 r o ------ - 1 k m r i ? -------------------- + ?? ?? 14.7k = ? = (eq. 19) f p 14.7k 2 ? -------------- - 2.34k = = ? l k m r i ? l -------------------- 24 0.037 ? 3.3 ? --------------------------- - 269k == = (eq. 20) f l 269k 2 ? ------------ - 42.83k = = f c 0.1f sw 30k == (eq. 21) c 2 r o r i k d ? ------------------ - 1 2 ? r 1 f c ------------------- - 0.97n = ? = (eq. 22) f z1 1 2 ? r 3 c 2 ---------------------- 2.34k = = f z2 1 2 ? r 1 c 1 ---------------------- 42.83k = = f p2 1 2 ? r 3 c 3 ---------------------- 100k == (eq. 23)
ISL8117A 20 fn8752.0 august 31, 2015 submit document feedback 9. use copper filled polygons or wide short traces to connect the junction of upper fet, lower fet and output inductor. also keep the phase node connection to the ic short. do not unnecessarily oversize the co pper islands for the phase node. since the phase nodes are subjected to very high dv/dt voltages, the stray capacitor formed between these islands and the surrounding circuitry will tend to couple switching noise. 10. route all high speed switchin g nodes away from the control circuitry. 11. create a separate small anal og ground plane near the ic. connect the sgnd pin to this pl ane. all small signal grounding paths including feedback resi stors, current limit setting resistor, soft-starting capacitor and en pull-down resistor should be connected to this sgnd plane. 12. separate the current sensing trace from the phase node connection. 13. ensure the feedback connection to the output capacitor is short and direct. general powerpad design considerations the following is an example of how to use vias to remove heat from the ic. it is recommended to fill the thermal pad area with vias. a typical via array fills the thermal pad footprint such that their centers are 3x the radius apart from each other. keep the vias small but not so small that their inside diam eter prevents solder wicking through during reflow. connect all vias to the ground plan e. it is important the vias have a low thermal resistance for ef ficient heat transfer. it is important to have a complete connection of the plated through-hole to each plane. component selection guideline mosfet considerations the logic level mosfets are chosen for optimum efficiency given the potentially wide input voltage range and output power requirement. two n-channel mosfets are used in the synchronous-rectified buck converters. these mosfets should be selected based upon r ds(on) , gate supply requirements and thermal management considerations. power dissipation includes two loss components: conduction loss and switching loss. these losses are distributed between the upper and lower mosfets according to duty cycle (see equations 24 and 25 ). the conduction losses are the main component of power dissipation for the lower mosfet. only the upper mosfet has significant switching losses since the lower device turns on and off into near zero voltage. the equations assume linear voltage current transitions and do not model power loss due to the reverse recovery of the lower mosfet?s body diode. a large gate-charge increases the switching time, t sw , which increases the upper mosfets? swit ching losses. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal resistance specifications. output inductor selection the pwm converter requires an output inductor. the output inductor is selected to meet the output voltage ripple requirements. the inductor value determines the converter?s ripple current and the ripple voltage is a function of the ripple current and the output capacitor(s) esr. the ripple voltage expression is given in the output capacitor selection section and the ripple current is approximated by equation 26 : the ripple current ratio is usually from 30% to 70% of the full output load. output capacitor selection the output capacitors for each output have unique requirements. in general, the output capacitors should be selected to meet the dynamic regulation requirements including ripple voltage and load transients. selection of output capacitors is also dependent on the output inductor, so some in ductor analysis is required to select the output capacitors. one of the parameters limiting the converter?s response to a load transient is the time required for the inductor current to slew to its new level. the ISL8117A will provide either 0% or maximum duty cycle in response to a load transient. the response time is the time interval required to slew the inductor current from an initial current value to the load current level. during this interval, the difference between the inductor current and the transient current level must be supplied by the output capacitor(s). minimizing the response time can minimize the output capacitance required. al so, if the load transient rise time is slower than the inductor response time, as in a hard drive or cd drive, it reduces the requirement on the output capacitor. figure 34. pcb via pattern p upper i o 2 ?? r ds on ?? ?? v out ?? v in --------------------------------------------------------------- i o ?? v in ?? t sw ?? f sw ?? 2 --------------------------------------------------------- - + = (eq. 24) p lower i o 2 ?? r ds on ?? ?? v in v out C ?? v in --------------------------------------------------------------- --------------- - = (eq. 25) ? i l v in v out C ?? v out ?? f sw ?? l ?? v in ?? --------------------------------------------------------- - = (eq. 26)
ISL8117A 21 fn8752.0 august 31, 2015 submit document feedback the maximum capacitor value required to provide the full, rising step, transient load current duri ng the response time of the inductor is shown in equation 27 : where c out is the output capacitor(s) required, l o is the output inductor, i tran is the transient load current step, v in is the input voltage, v o is output voltage and dv out is the drop in output voltage allowed during the load transient. high frequency capacitors initially supply the transient current and slow the load rate of change seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the esr (equivalent series resistance) an d voltage rating requirements as well as actual capacitance requirements. the output voltage ripple is due to the inductor ripple current and the esr of the output capacitors as defined by equation 28 : where ? i l is calculated in equation 26 . high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load circuitry for specific decoupling requirements. use only specialized low-esr capacitors intended for switching regulator applications for the bu lk capacitors. in most cases, multiple small case electrolytic capacitors perform better than a single large case capacitor. in conclusion, the output capaci tors must meet the following criteria: 1. they must have sufficient bulk capacitance to sustain the output voltage during a load transient while the output inductor current is slewing to the value of the load transient. 2. the esr must be sufficiently low to meet the desired output voltage ripple due to the output inductor current. the recommended output capacitor value for the ISL8117A is between 100f to 680f, to meet the stability criteria with external compensation. use of al uminum electrolytic (poscap) or tantalum type capacitors is recommended. use of low esr ceramic capacitors is possible with loop analysis to ensure stability. input capacitor selection the important parameters for the input capacitor(s) are the voltage rating and the rms current rating. for reliable operation, select input capacitors with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25x greater than the maximum input voltage and 1.5x is a conservative guideline. the ac rms input current varies with the load giving in equation 29 : where dc is duty cycle of the pwm. the maximum rms current supplied by the input capacitance occurs at v in = 2 x v out , dc = 50% as shown in equation 30 : use a mix of input bypass capacitors to control the voltage ripple across the mosfets. use ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the rms current. small ceramic capacitors can be placed very close to the mosfets to suppress the voltage induced in the parasitic circuit impedances. solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. these capacitors must be capable of handling the surge current at power-up. c out l o ?? i tran ?? 2 2v in v o C ?? dv out ?? ---------------------------------------------------------- - = (eq. 27) v ripple ? i l esr ?? = (eq. 28) i rms dc dc 2 C i o ? = (eq. 29) i rms 1 2 -- - i o ? = (eq. 30)
ISL8117A 22 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8752.0 august 31, 2015 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change august 31, 2015 fn8752.0 initial release
ISL8117A 23 fn8752.0 august 31, 2015 submit document feedback package outline drawing l16.4x4a 16 lead quad flat no-lead plastic package rev 3, 03/15 notes: 1. dimensions are in millimeters. dimensions in ( ) for reference only. 2. dimensioning and tolerancing conform to asme y14.5m-1994. 3. unless otherwise specified , tolerance: decimal 0.05 4. dimension applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. tiebar shown (if present) is a non-functional feature. 6. the configuration of the pin #1 identifier is optional, but m ust be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. top view index area (4x) 0.15 pin 1 6 4.00 4.00 a b see typical recommended land pattern 0.20 ref +0.03/-0.02 detail "x" c 5 side view bottom view 0.08 c c seating 0.10 c +0.05 pin #1 5 8 4 0.10 c m 12 9 4 0.50 12x 13 4x 1.50 16 1 6 a b ( 2.40) (12x 0.50) (16x 0.25) (3.8 typ) -0.07 0.25 0.900.10 2.40 16x 0.400.01 (16x 0.60) index area 2.40 detail "x" plane

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